Linear high-efficiency CMOS power amplifiers

Abbas Komijani (komijani@caltech.edu)

One of the major drawbacks to achieve the single-chip transceiver
implementation, is the integrated CMOS power amplifier. High output power
together with low-quality passive elements and continuous scaling and
consequently decrease of the breakdown voltage of CMOS transistors is one
side of the challenge. High efficiency needed for hand-held wireless
applications together with the need for linear power amplifiers with the
trend toward spectrum-efficient CDMA approach has made the other wall of the
design room. Supposed to breathe in this tiny room,the interference coupled
to other noise-sensitive elements of the transceiver, with signals having
dynamic range differences more than 100dB, has to be minimum in order to let
the other blocks survive.

So my research will be focused on circuits and techniques for linear and
high-efficiency integrated CMOS power amplifiers.