Ultrahigh Speed Integrated Circuits for Wire-line Data Communication
Introduction
Although the world of wireless communications dominates the individual
customer side of the transmit and receive path of communication channels, the dramatic
increase in the number of users forces Service Providers to exploit wire-line channels for
reliable high bit rate data transmission. In addition, the high demand for multimedia, a
complex of data, voice, and video, adds to the ever-increasing internet traffic, requiring a
new method for ultrahigh speed network communication. The evolution of optical
communications and optoelectronics has introduced a promising way to overcome this
problem. Optical networking standards such as SONET/SDH are well developed and
high speed communication systems like 2.5 Gb/sec (OC-48) and 10Gb/sec (OC-192) based on those are already deployed. In parallel, to add all the desired advantages of integrated circuits, efforts have been made to implement fully integrated optical communication systems in cheap and well-developed technologies primarily based on silicon technology, while keeping the system performance at reasonable levels.The current project vision is to develop fully integrated receiver and transmitter for optical communication purposes in 40 Gb/s and 160 Gb/s, based on SONET/SDH OC-768 and OC-3072 standards, respectively. There are several different blocks that are required, the most important of which are: The wideband transimpedance preamplifier, the automatic gain control stage (AGC), the clock and data recovery circuit (CDR), and the demultiplexers (DEMUX) at the receiver front end, and the front end multiplexer along with the wideband transadmittance driver amplifier at the transmitter. The major approach in the project is to browse through the problems from a more fundamental stand-point. The principal drawbacks of current system-level and circuit-level designs are thoroughly studied and novel methodologies are introduced which completely mitigate the undesirable effects. Based on this multidisciplinary approach, several circuits have been implemented, or are under development.
Transimpedance Amplifier
A CMOS transimpedance amplifier (TIA) is implemented using a new developed
technique to boost the bandwidth while keeping the gain of the amplifier at the same levels. The technique, namely multi-pole bandwidth enhancement, uses several passive elements to relocate the poles and zeros of a given architecture. With proper control of the locations of the poles and zeros, several desired amplitude/phase responses can be achieved. This will not depend on the transistor gain behavior and in principal the passives along with the transistor parasitics will control the response shape. Using 0.18um CMOS transistors, a 10 Gb/s TIA has been implemented with over 50dB-Ohm trans-impedance gain. This impressive result demonstrates the potential of CMOS technology, which is sometimes looked down upon. Using the same new methodology, a fully integrated SiGe 40 Gb/s TIA is implemented. The simulated bandwidth for over 1k-Ohm, is 31 GHz. The circuit measurement is under progress and primary results are completely in agreement with the simulations. Another approach for implementing very high speed TIAs is using the distributed circuit techniques. Distributed amplifiers have been known for over half a century. Making integrated distributed TIA (DTIA) is challenging, esp. due to the high quality required for artificial transmission lines. SiGe HBTs and novel CMOS SOI technologies offer high performance high speed transistors, along with better passive structures due to advanced process steps. Simple distributed architectures, an artwork of transistors and passives, has been accurately simulated using advanced E&M simulators over the layer properties of different technologies. It shows quite reasonable responses for integrated DTIAs. Some 40 GB/s DTIA samples are under development using short< channel CMOS technologies.
Data Recovery
Clock and Data Recovery (CDR) is a challenging part of designing a high-speed
communication network. Specifically, in 40 GB/s and higher data rates, meeting the requirements for clock jitter is not a trivial task. A novel approach is invented that has resulted in a new methodology for data recovery. The challenges are pushed to another domain of problems easier to solve. Semi-Synchronous nature of the method with only one unit interval (UI) of memory for the whole system makes it very fast with totally different intrinsic behavior compared to conventional CDR systems. In this project, we try to analyze and model the behavior of the system and make integrated prototypes on silicon and test their functionality and performance.
Interval Modulation Coding
This novel method of modulation and coding has been invented in ParaDiSe (Parallel and Distributed Systems) lab. at Caltech. The rate enhancement of this technique makes it a very promising candidate for future generation of very high-speed data communications. This method makes it possible to implement 80-100 GB/s with circuits operating at half the frequency or even lower. The asynchronous nature of the modulation requires a completely different system architecture and novel circuit level techniques that make it more interesting research area than just pushing for faster transistors. Transmitter and receiver prototypes are fabricated and the development is under progress.