High frequency CMOS voltage controlled oscillators and frequency synthesizers for wireless communications

Hui Wu (wu@caltech.edu)

 

I am currently participating in the 24 GHz Wireless LAN project at Caltech. The aim of this project is to develop a broadband network operating in the open ISM band at 24 GHz. Therefore, it can provide very large bandwidth for high data-rate communications, and enable the usage of a small size (~ 2 inches) phased array antenna for additional gain, diversity and selectivity.

Most efforts in this project are concentrated on a low-cost integrated transceiver, in which all RF and DSP circuitry will be integrated on a single silicon chip, with the exception of the antenna, low noise amplifier and power amplifier, which will be done with GaAs technology. The biggest challenge lies in the first up/down conversion stage between the 24 GHz RF and first IF, which requires a fully-integrated frequency synthesizer on silicon around 20 GHz (K-band). Such an ambitious goal can only be achieved through new and less-conventional techniques and methodologies. 

Since voltage controlled oscillators (VCO) and frequency dividers are the most crucial building blocks in such a high frequency, silicon-base frequency synthesizer, I began with the design of high frequency VCOs. Due to the lossy silicon substrate at high frequencies, it is impractical to implement a conventional LC-tank oscillator at such frequencies with CMOS technology. This obstacle can be mitigated by applying the idea of distributed circuitry as opposed to lumped circuitry. A distributed oscillator originates from distributed amplifiers, which offer a larger bandwidth in a given technology by trading delay for gain-bandwidth product. 

In order to realize a distributed voltage controlled oscillator (DVCO), a novel tuning technique, current-steering delay-balanced tuning was devised, for which a US patent has been filed. Using our new tuning technique and full-wave transmission line modeling, a 10 GHz CMOS DVCO was designed and fabricated in a 0.35 um CMOS technology with a tuning range of 12%. This prototype paves the way for an improved DVCO at 20 GHz. For verification purpose, a 12 GHz bipolar DVCO and a 17 GHz bipolar distributed oscillator have also been designed and tested. These results are reported in the following publications: 

Another part of my work is focused on the frequency divider, which is another critical component in a PLL-based frequency synthesizer. At high frequencies, its operation can lead to large power consumption, especially in the case of conventional flip-flop type frequency dividers. In order to achieve low-power operation, we have to explore new approaches. A promising candidate is an injection-locked frequency divider originally suggested by Rategh, et al, which has low power consumption due to its narrow bandwidth. The original approach is limited to a division ratio of two. We have been able to enhance and extend this technique to higher division ratios and larger locking range. 

The impact of such a low-cost, low-power, very high frequency CMOS RF front-end will go beyond the wireless LAN project itself. I believe that silicon has immense potential at very high frequencies that used to be achievable only by GaAs or other III-IV semiconductor technologies. Exploiting the full capabilities of silicon technology can open a new era of high frequency, low-cost, highly integrated circuits that can further advance the industry. I intend to explore these possibilities using innovative techniques such as distributed circuit design.